Constant advances of semiconductor manufacturing technology have greatly shrunken the size of electronic elements and also greatly reduced their production costs. Conventional semiconductor manufacturing techniques generally adopt an approach such as etching, ion implantation or routing on a substrate to form a planar semiconductor structure. These techniques now can fabricate a chip at a minimum size of 6F2. However, as developments of feature size have been gradually slowed down, area occupied by semiconductors on wafers cannot be significantly reduced. As a result, a vertical (also called three-dimensional) semiconductor manufacturing technology has been developed that aims to grow semiconductors vertically on the wafer to reduce the area occupied by transistors on the wafer surface and can further shrink the size of the chip to 4F2.
For instance, U.S. Pat. No. 7,326,611 entitled “DRAM arrays, vertical transistor structures and methods of forming transistor structure and DRAM Arrays” and U.S. publication No. 2005/0190617 entitled “Folded bit line DRAM with vertical ultra thin body transistors” disclose a vertical pillar transistor structure and method and process of manufacturing same. Please refer to FIG. 1 for a conventional vertical Dynamic Random Access Memory (DRAM) which has a pillar 1 and a gate material 2 next to the pillar 1 to control ON/OFF of the pillar 1 functioning as a transistor. The gate material 2 usually is formed by etching a metal wire to generate two pins to attach to two sides of the pillar 1 without contacting with each other but being connected via a conductive wire 3 so that a voltage can be applied to the pillar 1 for controlling ON or OFF thereof and data can be stored or read via a capacitor 4 located on the pillar 1. However, in the present technique, as the minimum feature size has been reduced to 40 nm, the thickness of metal wires and intervals between them also have to be shrunk to match the feature size. Especially since the interval between the metal wires has been shrunk from 45 nm to 15 nm in the 65 nm nanometer process, probably one third of the previously one, it creates a great challenge in terms of precise etching position and etching time duration. Thus how to efficiently fabricate the gate material 2 in response to gradually shrunken feature size has become an urgent issue in the semiconductor industry at present.